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| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:43 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:43 +0000 |
| commit | f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa (patch) | |
| tree | 15af740a873c04733c44402a39a4a18d8fb1c417 /lib/Target/ARM/ARMScheduleA9.td | |
| parent | fc992996f751e0941951b6d08d8f1e80ebec1385 (diff) | |
| download | llvm-f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa.tar.gz llvm-f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa.tar.bz2 llvm-f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa.tar.xz | |
ARM itinerary properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleA9.td')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleA9.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMScheduleA9.td b/lib/Target/ARM/ARMScheduleA9.td index 0d710cc1ac..a00577bf3d 100644 --- a/lib/Target/ARM/ARMScheduleA9.td +++ b/lib/Target/ARM/ARMScheduleA9.td @@ -31,7 +31,11 @@ def A9_DRegsN : FuncUnit; // FP register set, NEON side // Bypasses def A9_LdBypass : Bypass; -def CortexA9Itineraries : ProcessorItineraries< +def CortexA9Itineraries : MultiIssueItineraries< + 2, // IssueWidth - FIXME: A9_Issue0, A9_Issue1 are now redundant. + 0, // MinLatency - FIXME: for misched, remove InstrStage for OOO operations. + 2, // LoadLatency - optimistic, assumes bypass, overriden by OperandCycles. + 10, // HighLatency - currently unused. [A9_Issue0, A9_Issue1, A9_Branch, A9_ALU0, A9_ALU1, A9_AGU, A9_NPipe, A9_MUX0, A9_LSUnit, A9_DRegsVFP, A9_DRegsN], [A9_LdBypass], [ |