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author | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 04:42:00 +0000 |
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committer | Arnold Schwaighofer <aschwaighofer@apple.com> | 2013-04-05 04:42:00 +0000 |
commit | 08da4865576056f997a9c8013240d716018f7edf (patch) | |
tree | f99588a26e23f5554daa91c4393b8088eb19f222 /lib/Target/ARM/ARMScheduleSwift.td | |
parent | d4d7613af3fa3ba9abd7ea0828d9dadc23dd73ea (diff) | |
download | llvm-08da4865576056f997a9c8013240d716018f7edf.tar.gz llvm-08da4865576056f997a9c8013240d716018f7edf.tar.bz2 llvm-08da4865576056f997a9c8013240d716018f7edf.tar.xz |
ARM scheduler model: Swift has varying latencies, uops for simple ALU ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleSwift.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 44 |
1 files changed, 39 insertions, 5 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index 28bb429feb..4a87faaac0 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1083,6 +1083,9 @@ def SwiftModel : SchedMachineModel { let Itineraries = SwiftItineraries; } +// Swift predicates. +def IsFastImmShiftSwiftPred : SchedPredicate<[{TII->isSwiftFastImmShift(MI)}]>; + // Swift resource mapping. let SchedModel = SwiftModel in { // Processor resources. @@ -1092,15 +1095,46 @@ let SchedModel = SwiftModel in { def SwiftUnitP2 : ProcResource<1>; // LS unit. def SwiftUnitDiv : ProcResource<1>; + // Generic resource requirements. + def SwiftWriteP01TwoCycle : SchedWriteRes<[SwiftUnitP01]> { let Latency = 2; } + def SwiftWriteP01ThreeCycleTwoUops : + SchedWriteRes<[SwiftUnitP01, SwiftUnitP01]> { + let Latency = 3; + let NumMicroOps = 2; + } + def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> { + let Latency = 3; + let NumMicroOps = 3; + let ResourceCycles = [3]; + } + // 4.2.4 Arithmetic and Logical. + // ALU operation register shifted by immediate variant. + def SwiftWriteALUsi : SchedWriteVariant<[ + // lsl #2, lsl #1, or lsr #1. + SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>, + // Arbitrary imm shift. + SchedVar<NoSchedPred, [WriteALU]> + ]>; + def SwiftWriteALUsr : SchedWriteVariant<[ + SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>, + SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> + ]>; + def SwiftWriteALUSsr : SchedWriteVariant<[ + SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>, + SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]> + ]>; + def SwiftReadAdvanceALUsr : SchedReadVariant<[ + SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>, + SchedVar<NoSchedPred, [NoReadAdvance]> + ]>; // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR // AND,BIC, EOR,ORN,ORR // CLZ,RBIT,REV,REV16,REVSH,PKH - // Single cycle. def : WriteRes<WriteALU, [SwiftUnitP01]>; - def : WriteRes<WriteALUsi, [SwiftUnitP01]>; - def : WriteRes<WriteALUsr, [SwiftUnitP01]>; - def : WriteRes<WriteALUSsr, [SwiftUnitP01]>; + def : SchedAlias<WriteALUsi, SwiftWriteALUsi>; + def : SchedAlias<WriteALUsr, SwiftWriteALUsr>; + def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>; def : ReadAdvance<ReadALU, 0>; - def : ReadAdvance<ReadALUsr, 2>; + def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>; } |