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author | Andrew Trick <atrick@apple.com> | 2013-06-15 04:50:02 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-06-15 04:50:02 +0000 |
commit | a5ce5f36d3a1e312304e8312ca64a1342f5f55a6 (patch) | |
tree | 48b5f93d3c1ec9781977edafc9a09eb43673b8a9 /lib/Target/ARM/ARMScheduleSwift.td | |
parent | b86a0cdb674549d8493043331cecd9cbf53b80da (diff) | |
download | llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.tar.gz llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.tar.bz2 llvm-a5ce5f36d3a1e312304e8312ca64a1342f5f55a6.tar.xz |
Update machine models. Specify buffer sizes for OOO processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMScheduleSwift.td')
-rw-r--r-- | lib/Target/ARM/ARMScheduleSwift.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td index b5cf2518c0..2a41616b40 100644 --- a/lib/Target/ARM/ARMScheduleSwift.td +++ b/lib/Target/ARM/ARMScheduleSwift.td @@ -1076,7 +1076,7 @@ def SwiftItineraries : ProcessorItineraries< // Swift machine model for scheduling and other instruction cost heuristics. def SwiftModel : SchedMachineModel { let IssueWidth = 3; // 3 micro-ops are dispatched per cycle. - let MinLatency = 0; // Data dependencies are allowed within dispatch groups. + let MicroOpBufferSize = 45; // Based on NEON renamed registers. let LoadLatency = 3; let MispredictPenalty = 14; // A branch direction mispredict. |