ARM Scheduler Model: Add resources instructions, map resources in subtargets

Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177968 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 22 insertions, 1 deletions

diff --git a/lib/Target/ARM/ARMScheduleSwift.td b/lib/Target/ARM/ARMScheduleSwift.td
index e9bc3e0f39..becf41b0ef 100644
--- a/lib/Target/ARM/ARMScheduleSwift.td
+++ b/lib/Target/ARM/ARMScheduleSwift.td
@@ -1078,8 +1078,29 @@ def SwiftModel : SchedMachineModel {
   let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
   let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
   let LoadLatency = 3;
+  let MispredictPenalty = 14; // A branch direction mispredict.
 
   let Itineraries = SwiftItineraries;
 }
 
-// TODO: Add Swift processor and scheduler resources.
+// Swift resource mapping.
+let SchedModel = SwiftModel in {
+  // Processor resources.
+  def SwiftUnitP01 : ProcResource<2>; // ALU unit.
+  def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit.
+  def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit.
+  def SwiftUnitP2 : ProcResource<1>; // LS unit.
+  def SwiftUnitDiv : ProcResource<1>;
+
+  // 4.2.4 Arithmetic and Logical.
+  // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
+  // AND,BIC, EOR,ORN,ORR
+  // CLZ,RBIT,REV,REV16,REVSH,PKH
+  // Single cycle.
+  def : WriteRes<WriteALU, [SwiftUnitP01]>;
+  def : WriteRes<WriteALUsi, [SwiftUnitP01]>;
+  def : WriteRes<WriteALUsr, [SwiftUnitP01]>;
+  def : WriteRes<WriteALUSsr, [SwiftUnitP01]>;
+  def : ReadAdvance<ReadAdvanceALU, 0>;
+  def : ReadAdvance<ReadAdvanceALUsr, 2>;
+}