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author | Evan Cheng <evan.cheng@apple.com> | 2012-12-20 19:59:30 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2012-12-20 19:59:30 +0000 |
commit | 139e407d526193017d42473c8d4892933de78f14 (patch) | |
tree | 37f08e11f0f3c4c2944880253feea017e2146aba /lib/Target/ARM/ARMSubtarget.h | |
parent | 15019a8814b7877367ca7bcd7d173710259f7c20 (diff) | |
download | llvm-139e407d526193017d42473c8d4892933de78f14.tar.gz llvm-139e407d526193017d42473c8d4892933de78f14.tar.bz2 llvm-139e407d526193017d42473c8d4892933de78f14.tar.xz |
On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,
are more expensive than the non-flag setting variant. Teach thumb2 size
reduction pass to avoid generating them unless we are optimizing for size.
rdar://12892707
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMSubtarget.h')
-rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index c7e3adcb51..b96e738a6c 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -131,6 +131,10 @@ protected: /// CPSR setting instruction. bool AvoidCPSRPartialUpdate; + /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting + /// movs with shifter operand (i.e. asr, lsl, lsr). + bool AvoidMOVsShifterOperand; + /// HasRAS - Some processors perform return stack prediction. CodeGen should /// avoid issue "normal" call instructions to callees which do not return. bool HasRAS; @@ -232,6 +236,7 @@ protected: bool isFPOnlySP() const { return FPOnlySP; } bool prefers32BitThumb() const { return Pref32BitThumb; } bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } + bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } bool hasRAS() const { return HasRAS; } bool hasMPExtension() const { return HasMPExtension; } bool hasThumb2DSP() const { return Thumb2DSP; } |