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| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-16 08:38:26 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-16 08:38:26 +0000 |
| commit | b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 (patch) | |
| tree | a891fa0a8cb7d5f75446fc0f0346eb55b18a715c /lib/Target/ARM/ARMTargetMachine.h | |
| parent | f1b41dd38d2b2713e3870f384525b020bbac05f6 (diff) | |
| download | llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.gz llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.bz2 llvm-b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16.tar.xz | |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/ARMTargetMachine.h')
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.h | 22 |
1 files changed, 12 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index c8c601c301..a1f517b0f4 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -41,7 +41,8 @@ private: public: ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -50,13 +51,12 @@ public: } // Pass Pipeline Configuration - virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel); - virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel, - JITCodeEmitter &MCE); + virtual bool addPreISel(PassManagerBase &PM); + virtual bool addInstSelector(PassManagerBase &PM); + virtual bool addPreRegAlloc(PassManagerBase &PM); + virtual bool addPreSched2(PassManagerBase &PM); + virtual bool addPreEmitPass(PassManagerBase &PM); + virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE); }; /// ARMTargetMachine - ARM target machine. @@ -71,7 +71,8 @@ class ARMTargetMachine : public ARMBaseTargetMachine { public: ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -111,7 +112,8 @@ class ThumbTargetMachine : public ARMBaseTargetMachine { public: ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { |