diff options
| author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 13:28:17 +0000 |
|---|---|---|
| committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-27 13:28:17 +0000 |
| commit | cca114611945332852094fcadfaa4ffbd012bfb3 (patch) | |
| tree | 96aeb92bfbe577c6bd513fcfa69877be972c913a /lib/Target/ARM/AsmParser | |
| parent | 9f30d43122dce961ae1625c2c429bf74bf292324 (diff) | |
| download | llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.gz llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.bz2 llvm-cca114611945332852094fcadfaa4ffbd012bfb3.tar.xz | |
ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:
LDRD<c> <Rt>, <Rt2>, ...
(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)
If those two constraints are not met the result of executing the instruction will be unpredictable.
Constraint (b) was already enforced, this commit adds support for constraint (a).
Fixes rdar://14479793.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/AsmParser')
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 14063eac1f..6d6255f2cc 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5347,8 +5347,17 @@ validateInstruction(MCInst &Inst, case ARM::LDRD: case ARM::LDRD_PRE: case ARM::LDRD_POST: { + unsigned RtReg = Inst.getOperand(0).getReg(); + // Rt can't be R14. + if (RtReg == ARM::LR) + return Error(Operands[3]->getStartLoc(), + "Rt can't be R14"); + unsigned Rt = MRI->getEncodingValue(RtReg); + // Rt must be even-numbered. + if ((Rt & 1) == 1) + return Error(Operands[3]->getStartLoc(), + "Rt must be even-numbered"); // Rt2 must be Rt + 1. - unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); if (Rt2 != Rt + 1) return Error(Operands[3]->getStartLoc(), |