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authorJim Grosbach <grosbach@apple.com>2011-11-30 18:21:25 +0000
committerJim Grosbach <grosbach@apple.com>2011-11-30 18:21:25 +0000
commit13af222bab6fdc77d8193eb38e78a9cbed1d9d1f (patch)
tree96cebac821b4d37db7b673d1939f7b47b69ee1bf /lib/Target/ARM/InstPrinter
parent78647434ea861806f0c75ef20afe12f3ff6dbbec (diff)
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ARM parsing for VLD1 two register all lanes, no writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145504 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/InstPrinter')
-rw-r--r--lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp9
-rw-r--r--lib/Target/ARM/InstPrinter/ARMInstPrinter.h2
2 files changed, 11 insertions, 0 deletions
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index ed2594e2ae..827883dd49 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -1036,3 +1036,12 @@ void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
}
+void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
+ unsigned OpNum,
+ raw_ostream &O) {
+ // Normally, it's not safe to use register enum values directly with
+ // addition to get the next register, but for VFP registers, the
+ // sort order is guaranteed because they're all of the form D<n>.
+ O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
+ << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[]}";
+}
diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
index e25fc7c199..b1fe9a142f 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
@@ -135,6 +135,8 @@ public:
void printVectorListFour(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printVectorListOneAllLanes(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
+ void printVectorListTwoAllLanes(const MCInst *MI, unsigned OpNum,
+ raw_ostream &O);
};
} // end namespace llvm