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| author | Evan Cheng <evan.cheng@apple.com> | 2007-03-20 22:32:39 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-03-20 22:32:39 +0000 |
| commit | a125cbe839398f7df475e322bdaf150c62a1c8c3 (patch) | |
| tree | 08f23765bdbc41738fb9aa6a59ed859294527142 /lib/Target/ARM/README.txt | |
| parent | c3c70881cf7457535182add96d0ea96a3a12e9f2 (diff) | |
| download | llvm-a125cbe839398f7df475e322bdaf150c62a1c8c3.tar.gz llvm-a125cbe839398f7df475e322bdaf150c62a1c8c3.tar.bz2 llvm-a125cbe839398f7df475e322bdaf150c62a1c8c3.tar.xz | |
Updated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35229 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/README.txt')
| -rw-r--r-- | lib/Target/ARM/README.txt | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index c155e20633..8af07ccffb 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -470,4 +470,9 @@ More register scavenging work: //===---------------------------------------------------------------------===// -Teach LSR about ARM addressing modes. +More LSR enhancements possible: + +1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged + in a load / store. +2. Allow iv reuse even when a type conversion is required. For example, i8 + and i32 load / store addressing modes are identical. |