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author | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 21:49:47 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2007-07-10 21:49:47 +0000 |
commit | c608ff22e79bf56b7227e56eb9e88fed2258b5c6 (patch) | |
tree | 19228ef7dec28d0cf7249f10649b511a159c194c /lib/Target/ARM/README.txt | |
parent | bf6b8272b1648eabb1e3b6e8b1abc62fdc648415 (diff) | |
download | llvm-c608ff22e79bf56b7227e56eb9e88fed2258b5c6.tar.gz llvm-c608ff22e79bf56b7227e56eb9e88fed2258b5c6.tar.bz2 llvm-c608ff22e79bf56b7227e56eb9e88fed2258b5c6.tar.xz |
Update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38513 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/README.txt')
-rw-r--r-- | lib/Target/ARM/README.txt | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt index c30c0e5a9f..3db8f54f50 100644 --- a/lib/Target/ARM/README.txt +++ b/lib/Target/ARM/README.txt @@ -7,7 +7,6 @@ Reimplement 'select' in terms of 'SEL'. * We would really like to support UXTAB16, but we need to prove that the add doesn't need to overflow between the two 16-bit chunks. -* implement predication support * Implement pre/post increment support. (e.g. PR935) * Coalesce stack slots! * Implement smarter constant generation for binops with large immediates. @@ -44,16 +43,12 @@ consecutive islands as a single block rather than multiple blocks. //===---------------------------------------------------------------------===// -We need to start generating predicated instructions. The .td files have a way -to express this now (see the PPC conditional return instruction), but the -branch folding pass (or a new if-cvt pass) should start producing these, at -least in the trivial case. +Eliminate copysign custom expansion. We are still generating crappy code with +default expansion + if-conversion. -Among the obvious wins, doing so can eliminate the need to custom expand -copysign (i.e. we won't need to custom expand it to get the conditional -negate). +//===---------------------------------------------------------------------===// -This allows us to eliminate one instruction from: +Eliminate one instruction from: define i32 @_Z6slow4bii(i32 %x, i32 %y) { %tmp = icmp sgt i32 %x, %y @@ -66,6 +61,12 @@ __Z6slow4bii: movgt r1, r0 mov r0, r1 bx lr +=> + +__Z6slow4bii: + cmp r0, r1 + movle r0, r1 + bx lr //===---------------------------------------------------------------------===// |