ARM: Add GPR register class excluding LR for use with the ADR instruction.

This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target.

Patch by Daniel Stewart!
   


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 14 insertions, 2 deletions

diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 286eaa0946..7c51c70f67 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -152,7 +152,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
     // otherwise).
     MachineRegisterInfo *MRI = &MF.getRegInfo();
-    MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
+    const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC,
+                                &ARM::rGPRRegClass,
+                                ARM::gsub_1);
+    assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass");
+    const TargetRegisterClass* ConstrainedClass =
+                                MRI->constrainRegClass(SrcReg, TargetClass);
+    assert(ConstrainedClass && "Couldn't constrain the register class");
 
     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
     AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
@@ -193,7 +199,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
     // gsub_0, but needs an extra constraint for gsub_1 (which could be sp
     // otherwise).
     MachineRegisterInfo *MRI = &MF.getRegInfo();
-    MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass);
+    const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC,
+                                &ARM::rGPRRegClass,
+                                ARM::gsub_1);
+    assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass");
+    const TargetRegisterClass* ConstrainedClass =
+                                MRI->constrainRegClass(DestReg, TargetClass);
+    assert(ConstrainedClass && "Couldn't constrain the register class");
 
     MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);