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authorOwen Anderson <resistor@mac.com>2011-08-11 21:52:38 +0000
committerOwen Anderson <resistor@mac.com>2011-08-11 21:52:38 +0000
commit796d6b7602f0279b52ff5c105fb73fbdf444f030 (patch)
tree8c4c11972715d9acb2ffd423c949827ad51ededf /lib/Target/ARM/Thumb2InstrInfo.cpp
parent05b0c9f41e7c6a091bacdfc1472f99ef204ee00e (diff)
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Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2InstrInfo.cpp')
-rw-r--r--lib/Target/ARM/Thumb2InstrInfo.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp
index 33fa5213be..bc104ebc78 100644
--- a/lib/Target/ARM/Thumb2InstrInfo.cpp
+++ b/lib/Target/ARM/Thumb2InstrInfo.cpp
@@ -122,7 +122,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
- RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
+ RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
+ RC == ARM::GPRnopcRegisterClass) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();
@@ -149,7 +150,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
- RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
+ RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
+ RC == ARM::GPRnopcRegisterClass) {
DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc();