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| author | David Goodwin <david_goodwin@apple.com> | 2009-07-08 18:31:39 +0000 |
|---|---|---|
| committer | David Goodwin <david_goodwin@apple.com> | 2009-07-08 18:31:39 +0000 |
| commit | db5a71a8e01ed9a0d93a19176df6ea0aea510d7b (patch) | |
| tree | b35e18b95964de09ec536f48255e3f1c283acea0 /lib/Target/ARM/Thumb2RegisterInfo.cpp | |
| parent | 205a5ca6cfabc6cd408634a2fa7f2529956cc2cf (diff) | |
| download | llvm-db5a71a8e01ed9a0d93a19176df6ea0aea510d7b.tar.gz llvm-db5a71a8e01ed9a0d93a19176df6ea0aea510d7b.tar.bz2 llvm-db5a71a8e01ed9a0d93a19176df6ea0aea510d7b.tar.xz | |
Push methods into base class in preparation for sharing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2RegisterInfo.cpp')
| -rw-r--r-- | lib/Target/ARM/Thumb2RegisterInfo.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp index 42d39a6f69..c1326e60e1 100644 --- a/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -38,7 +38,7 @@ Thumb2RegScavenging("enable-thumb2-reg-scavenging", cl::Hidden, cl::desc("Enable register scavenging on Thumb-2")); -Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii, +Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) : ARMBaseRegisterInfo(tii, sti) { } @@ -47,9 +47,10 @@ Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii, /// specified immediate. void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, + const TargetInstrInfo *TII, DebugLoc dl, unsigned DestReg, int Val, - const TargetInstrInfo *TII, - DebugLoc dl) const { + ARMCC::CondCodes Pred, + unsigned PredReg) const { MachineFunction &MF = *MBB.getParent(); MachineConstantPool *ConstantPool = MF.getConstantPool(); Constant *C = ConstantInt::get(Type::Int32Ty, Val); @@ -130,7 +131,7 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg) .addReg(LdReg, RegState::Kill); } else - MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl); + MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes); // Emit add / sub. int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); @@ -504,7 +505,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl); + emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset); UseRR = true; } } else @@ -542,7 +543,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg, Offset, false, TII, *this, dl); else { - emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl); + emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset); UseRR = true; } } else |