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authorJim Grosbach <grosbach@apple.com>2012-02-24 00:53:11 +0000
committerJim Grosbach <grosbach@apple.com>2012-02-24 00:53:11 +0000
commitd1b220a33b16d97ef4194b4da625ba1c57974dee (patch)
tree694334e7c6a693e8d0837bc584cb92243c121c08 /lib/Target/ARM/Thumb2SizeReduction.cpp
parentfdf7c850321bba542e181ae035507d9c71d95364 (diff)
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Make sure the regs are low regs for tMUL size reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Thumb2SizeReduction.cpp')
-rw-r--r--lib/Target/ARM/Thumb2SizeReduction.cpp7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/Thumb2SizeReduction.cpp b/lib/Target/ARM/Thumb2SizeReduction.cpp
index 776d0eff5e..5ee5f4202e 100644
--- a/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ b/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -599,7 +599,12 @@ Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned Reg1 = MI->getOperand(1).getReg();
// t2MUL is "special". The tied source operand is second, not first.
if (MI->getOpcode() == ARM::t2MUL) {
- if (Reg0 != MI->getOperand(2).getReg()) {
+ unsigned Reg2 = MI->getOperand(2).getReg();
+ // Early exit if the regs aren't all low regs.
+ if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
+ || !isARMLowRegister(Reg2))
+ return false;
+ if (Reg0 != Reg2) {
// If the other operand also isn't the same as the destination, we
// can't reduce.
if (Reg1 != Reg0)