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author | Bill Wendling <isanbard@gmail.com> | 2013-06-07 06:19:56 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2013-06-07 06:19:56 +0000 |
commit | 54a56fad36a32f12709da5f96998336f08524be9 (patch) | |
tree | b8ff9ae26a5ebd885ba1a05b8b9934b04bca9e6e /lib/Target/Hexagon/HexagonCallingConvLower.cpp | |
parent | 9eb856bc295eabe1ebff0325158e65050deddd56 (diff) | |
download | llvm-54a56fad36a32f12709da5f96998336f08524be9.tar.gz llvm-54a56fad36a32f12709da5f96998336f08524be9.tar.bz2 llvm-54a56fad36a32f12709da5f96998336f08524be9.tar.xz |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183490 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonCallingConvLower.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonCallingConvLower.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/Hexagon/HexagonCallingConvLower.cpp b/lib/Target/Hexagon/HexagonCallingConvLower.cpp index 2c93d04f98..fc5503aae2 100644 --- a/lib/Target/Hexagon/HexagonCallingConvLower.cpp +++ b/lib/Target/Hexagon/HexagonCallingConvLower.cpp @@ -27,12 +27,11 @@ Hexagon_CCState::Hexagon_CCState(CallingConv::ID CC, bool isVarArg, const TargetMachine &tm, SmallVector<CCValAssign, 16> &locs, LLVMContext &c) - : CallingConv(CC), IsVarArg(isVarArg), TM(tm), - TRI(*TM.getRegisterInfo()), Locs(locs), Context(c) { + : CallingConv(CC), IsVarArg(isVarArg), TM(tm), Locs(locs), Context(c) { // No stack is used. StackOffset = 0; - UsedRegs.resize((TRI.getNumRegs()+31)/32); + UsedRegs.resize((TM.getRegisterInfo()->getNumRegs()+31)/32); } // HandleByVal - Allocate a stack slot large enough to pass an argument by @@ -56,6 +55,7 @@ void Hexagon_CCState::HandleByVal(unsigned ValNo, EVT ValVT, /// MarkAllocated - Mark a register and all of its aliases as allocated. void Hexagon_CCState::MarkAllocated(unsigned Reg) { + const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) UsedRegs[*AI/32] |= 1 << (*AI&31); } |