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authorCraig Topper <craig.topper@gmail.com>2012-04-20 07:30:17 +0000
committerCraig Topper <craig.topper@gmail.com>2012-04-20 07:30:17 +0000
commit420761a0f193e87d08ee1c51b26bba23ab4bac7f (patch)
tree55aa0936b18927fe72fb4806eeab177b42c2f9cd /lib/Target/Hexagon/HexagonHardwareLoops.cpp
parentc909950c384e8234a7b3c5a76b7f79e3f7012ceb (diff)
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Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonHardwareLoops.cpp')
-rw-r--r--lib/Target/Hexagon/HexagonHardwareLoops.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 57772a514d..c31cf43a11 100644
--- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -623,7 +623,7 @@ void HexagonFixupHwLoops::convertLoopInstr(MachineFunction &MF,
const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
MachineBasicBlock *MBB = MII->getParent();
DebugLoc DL = MII->getDebugLoc();
- unsigned Scratch = RS.scavengeRegister(Hexagon::IntRegsRegisterClass, MII, 0);
+ unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0);
// First, set the LC0 with the trip count.
if (MII->getOperand(1).isReg()) {