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author | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-28 19:44:04 +0000 |
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committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-28 19:44:04 +0000 |
commit | 810848d5b3bc53747722db0d30a21dc168c5503e (patch) | |
tree | 52a9d19378de97165ce009fea7413dcdbf1b2f39 /lib/Target/Hexagon/HexagonInstrInfo.td | |
parent | b52980be0788a907c98fc08de090ad61aef86716 (diff) | |
download | llvm-810848d5b3bc53747722db0d30a21dc168c5503e.tar.gz llvm-810848d5b3bc53747722db0d30a21dc168c5503e.tar.bz2 llvm-810848d5b3bc53747722db0d30a21dc168c5503e.tar.xz |
Hexagon: Replace switch-case in isDotNewInst with TSFlags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.td')
-rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.td | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index d9d5425ebe..74dc0ca72a 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -508,29 +508,30 @@ def : Pat <(sext_inreg (i32 IntRegs:$src1), i16), //===----------------------------------------------------------------------===// // Conditional combine. -let neverHasSideEffects = 1, isPredicated = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in { def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1, isPredicated = 1 in +let isPredicatedFalse = 1 in def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1, isPredicated = 1 in +let isPredicatedNew = 1 in def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1, isPredicated = 1 in +let isPredicatedNew = 1, isPredicatedFalse = 1 in def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = combine($src2, $src3)", []>; +} // Compare. defm CMPGTU : CMP32_rr_ri_u9<"cmp.gtu", "CMPGTU", setugt>, ImmRegRel; |