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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-11-07 17:15:06 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-11-07 17:15:06 +0000 |
| commit | 6534f83ae8c39284ae51fbf478ce0c37d0c892a2 (patch) | |
| tree | bc7f6b5215bd2a3162233cd58983bc1fc482e36f /lib/Target/MSP430/MSP430InstrInfo.td | |
| parent | 8983da729aa1ca99a11a3b98ae6280dfcdbadb39 (diff) | |
| download | llvm-6534f83ae8c39284ae51fbf478ce0c37d0c892a2.tar.gz llvm-6534f83ae8c39284ae51fbf478ce0c37d0c892a2.tar.bz2 llvm-6534f83ae8c39284ae51fbf478ce0c37d0c892a2.tar.xz | |
Add some dummy support for post-incremented loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86385 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430InstrInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430InstrInfo.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index 2b50669198..6d7b87c362 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -215,6 +215,13 @@ def MOVZX16rm8 : Pseudo<(outs GR16:$dst), (ins memsrc:$src), "mov.b\t{$src, $dst}", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>; +let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in { +def MOV8rm_POST : Pseudo<(outs GR8:$dst, GR16:$base_wb), (ins GR16:$base), + "mov.b\t{@$base+, $dst}", []>; +def MOV16rm_POST : Pseudo<(outs GR16:$dst, GR16:$base_wb), (ins GR16:$base), + "mov.w\t{@$base+, $dst}", []>; +} + // Any instruction that defines a 8-bit result leaves the high half of the // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may // be copying from a truncate, but any other 8-bit operation will zero-extend |