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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-01-15 21:18:18 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-01-15 21:18:18 +0000 |
| commit | cb50e0bd60167440e2e41274f9d3c3c0e88d90ad (patch) | |
| tree | 84328eab0ce75de8c22b303aed4f93623c934369 /lib/Target/MSP430/MSP430InstrInfo.td | |
| parent | 0c1ba91a54e7088fab3a3b9820f8b8366be0e11b (diff) | |
| download | llvm-cb50e0bd60167440e2e41274f9d3c3c0e88d90ad.tar.gz llvm-cb50e0bd60167440e2e41274f9d3c3c0e88d90ad.tar.bz2 llvm-cb50e0bd60167440e2e41274f9d3c3c0e88d90ad.tar.xz | |
Enable bit tests and setcc stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93552 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430InstrInfo.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430InstrInfo.td | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td index 022d171f35..06a039fd66 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.td +++ b/lib/Target/MSP430/MSP430InstrInfo.td @@ -861,58 +861,60 @@ def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2), let isCommutable = 1 in { def BIT8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, GR8:$src2)), + [(MSP430cmp (and_su GR8:$src1, GR8:$src2), 0), (implicit SRW)]>; def BIT16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, GR16:$src2)), + [(MSP430cmp (and_su GR16:$src1, GR16:$src2), 0), (implicit SRW)]>; } def BIT8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, imm:$src2)), + [(MSP430cmp (and_su GR8:$src1, imm:$src2), 0), (implicit SRW)]>; def BIT16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, imm:$src2)), + [(MSP430cmp (and_su GR16:$src1, imm:$src2), 0), (implicit SRW)]>; def BIT8rm : Pseudo<(outs), (ins GR8:$src1, memdst:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR8:$src1, (load addr:$src2))), + [(MSP430cmp (and_su GR8:$src1, (load addr:$src2)), 0), (implicit SRW)]>; def BIT16rm : Pseudo<(outs), (ins GR16:$src1, memdst:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su GR16:$src1, (load addr:$src2))), + [(MSP430cmp (and_su GR16:$src1, (load addr:$src2)), 0), (implicit SRW)]>; def BIT8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), GR8:$src2)), + [(MSP430cmp (and_su (load addr:$src1), GR8:$src2), 0), (implicit SRW)]>; def BIT16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), GR16:$src2)), + [(MSP430cmp (and_su (load addr:$src1), GR16:$src2), 0), (implicit SRW)]>; def BIT8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), (i8 imm:$src2))), + [(MSP430cmp (and_su (load addr:$src1), (i8 imm:$src2)), 0), (implicit SRW)]>; def BIT16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (load addr:$src1), (i16 imm:$src2))), + [(MSP430cmp (and_su (load addr:$src1), (i16 imm:$src2)), 0), (implicit SRW)]>; def BIT8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), "bit.b\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (i8 (load addr:$src1)), - (load addr:$src2))), + [(MSP430cmp (and_su (i8 (load addr:$src1)), + (load addr:$src2)), + 0), (implicit SRW)]>; def BIT16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), "bit.w\t{$src2, $src1}", - [(MSP430cmp 0, (and_su (i16 (load addr:$src1)), - (load addr:$src2))), + [(MSP430cmp (and_su (i16 (load addr:$src1)), + (load addr:$src2)), + 0), (implicit SRW)]>; } // Defs = [SRW] @@ -923,7 +925,8 @@ def BIT16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2), def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>; // anyext -def : Pat<(anyext addr:$src), (MOVZX16rr8 GR8:$src)>; +def : Pat<(i16 (anyext GR8:$src)), + (SUBREG_TO_REG (i16 0), GR8:$src, subreg_8bit)>; // truncs def : Pat<(i8 (trunc GR16:$src)), @@ -996,6 +999,6 @@ def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst), // peephole patterns def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>; -def : Pat<(MSP430cmp 0, (trunc (and_su GR16:$src1, GR16:$src2))), +def : Pat<(MSP430cmp (trunc (and_su GR16:$src1, GR16:$src2)), 0), (BIT8rr (EXTRACT_SUBREG GR16:$src1, subreg_8bit), (EXTRACT_SUBREG GR16:$src2, subreg_8bit))>; |