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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-04 03:30:34 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-04 03:30:34 +0000
commit338607ae0ddab00e197222e769748e2e0c0b4e18 (patch)
treeae0cdec113d5fb087b1bf0eccaecfdfae2432542 /lib/Target/MSP430
parent7855ec62c3b6b5b7e6d3fada589511abd964fdb3 (diff)
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Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430')
-rw-r--r--lib/Target/MSP430/MSP430RegisterInfo.td6
1 files changed, 1 insertions, 5 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index 3f2eb8ccef..07619d0675 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -78,8 +78,4 @@ def GR16 : RegisterClass<"MSP430", [i16], 16,
// Frame pointer, sometimes allocable
FPW,
// Volatile, but not allocable
- PCW, SPW, SRW, CGW)>
-{
- let SubRegClasses = [(GR8 subreg_8bit)];
-}
-
+ PCW, SPW, SRW, CGW)>;