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author | Reed Kotler <rkotler@mips.com> | 2013-02-08 21:42:56 +0000 |
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committer | Reed Kotler <rkotler@mips.com> | 2013-02-08 21:42:56 +0000 |
commit | b2d1275188c997e279293afc031a88e03871f9e0 (patch) | |
tree | d5485c78d40559571b34dd139dbe94646c8dc2d4 /lib/Target/Mips/Mips16InstrInfo.td | |
parent | 089a5f8a8c5e24f996dd41419de2c7bc7b42ea29 (diff) | |
download | llvm-b2d1275188c997e279293afc031a88e03871f9e0.tar.gz llvm-b2d1275188c997e279293afc031a88e03871f9e0.tar.bz2 llvm-b2d1275188c997e279293afc031a88e03871f9e0.tar.xz |
Add the 16 bit version of addiu. To the assembler, the 16 and 32 bit are the
same so we put in the comment field an indicator when we think we are
emitting the 16 bit version. For the direct object emitter, the difference is
important as well as for other passes which need an accurate count of
program size. There will be other similar putbacks to this for various
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174747 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
-rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 135df75693..49048db7b4 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -32,6 +32,18 @@ def mem16_ea : Operand<i32> { } // +// RI instruction format +// + + +class F2RI16_ins<bits<5> _op, string asmstr, + InstrItinClass itin>: + FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm), + !strconcat(asmstr, "\t$rx, $imm\t# 16 bit inst"), [], itin> { + let Constraints = "$rx_ = $rx"; +} + +// // Compare a register and immediate and place result in CC // Implicit use of T8 // @@ -416,6 +428,10 @@ class MayStore { // def AddiuRxImmX16: FEXT_RI16_ins<0b01001, "addiu", IIAlu>; +def AddiuRxRxImm16: F2RI16_ins<0b01001, "addiu", IIAlu>, + ArithLogic16Defs<0> { + let AddedComplexity = 5; +} def AddiuRxRxImmX16: FEXT_2RI16_ins<0b01001, "addiu", IIAlu>, ArithLogic16Defs<0>; @@ -1055,6 +1071,7 @@ class ArithLogicI16_pat<SDNode OpNode, PatFrag imm_type, Instruction I> : Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm), (I CPU16Regs:$in, imm_type:$imm)>; +def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>; def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>; def: ArithLogicI16_pat<shl, immZExt5, SllX16>; def: ArithLogicI16_pat<srl, immZExt5, SrlX16>; |