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| author | Reed Kotler <rkotler@mips.com> | 2013-02-18 00:59:04 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-02-18 00:59:04 +0000 |
| commit | da4afa72f7cbe2801f3876eda33416aa3ba42987 (patch) | |
| tree | 6d925707f9fe4a4cc33b8886535346ce2f1d769d /lib/Target/Mips/Mips16InstrInfo.td | |
| parent | 774ec7ba05606925966899d7dbe30453a3a2a877 (diff) | |
| download | llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.tar.gz llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.tar.bz2 llvm-da4afa72f7cbe2801f3876eda33416aa3ba42987.tar.xz | |
Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips16InstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/Mips16InstrInfo.td | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index ea4bbe844c..2ab7b47724 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -516,7 +516,9 @@ def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16; // Purpose: Branch on T Equal to Zero (Extended) // To test special register T then do a PC-relative conditional branch. // -def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16; +def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16 { + let Uses = [T8]; +} def BteqzT8CmpX16: FEXT_T8I816_ins<"bteqz", "cmp">, cbranch16; @@ -537,7 +539,9 @@ def BteqzT8SltiuX16: FEXT_T8I8I16_ins<"bteqz", "sltiu">, // Purpose: Branch on T Not Equal to Zero (Extended) // To test special register T then do a PC-relative conditional branch. // -def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16; +def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16 { + let Uses = [T8]; +} def BtnezT8CmpX16: FEXT_T8I816_ins<"btnez", "cmp">, cbranch16; @@ -553,6 +557,16 @@ def BtnezT8SltiuX16: FEXT_T8I8I16_ins<"btnez", "sltiu">, cbranch16; // +// Format: CMP rx, ry MIPS16e +// Purpose: Compare +// To compare the contents of two GPRs. +// +def CmpRxRy16: FRR16_ins<0b01010, "cmp", IIAlu> { + let Defs = [T8]; +} + + +// // Format: DIV rx, ry MIPS16e // Purpose: Divide Word // To divide 32-bit signed integers. |