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author | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:21:37 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-15 01:21:37 +0000 |
commit | 397f6da28cc889597e8c267e15154f1f70a0922a (patch) | |
tree | fbe46d4bbd84f85ba67131c955c50deba3c24482 /lib/Target/Mips/MipsDSPInstrInfo.td | |
parent | adb1297d49dd345821d7aa91057a0b22e6209a16 (diff) | |
download | llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.gz llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.bz2 llvm-397f6da28cc889597e8c267e15154f1f70a0922a.tar.xz |
[mips] Use predicates to guard instructions using accumulator registers instead
of relying on AddedComplexity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192665 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsDSPInstrInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrInfo.td | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index f511d0d73a..fd4ab5a292 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -453,7 +453,6 @@ class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt"); list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))]; InstrItinClass Itinerary = itin; - int AddedComplexity = 20; bit isCommutable = 1; } @@ -465,7 +464,6 @@ class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; InstrItinClass Itinerary = itin; - int AddedComplexity = 20; string Constraints = "$acin = $ac"; } @@ -476,7 +474,6 @@ class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode, string AsmString = !strconcat(instr_asm, "\t$rd, $ac"); list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))]; InstrItinClass Itinerary = itin; - int AddedComplexity = 20; } class MTHI_DESC_BASE<string instr_asm, RegisterOperand RO, InstrItinClass itin> { |