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authorAkira Hatanaka <ahatanaka@mips.com>2013-04-12 22:24:52 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-04-12 22:24:52 +0000
commit6d224459f42fd1e2a57479b6b60e55053dce38d7 (patch)
tree7f019a688d05e9c4de387507329bd864e81d32df /lib/Target/Mips/MipsDSPInstrInfo.td
parent9367b8d4f254d9e5cccb15334cc1a969c5be0d31 (diff)
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[mips] Instruction selection patterns for carry-setting and using add
instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179421 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsDSPInstrInfo.td')
-rw-r--r--lib/Target/Mips/MipsDSPInstrInfo.td8
1 files changed, 6 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td
index 2f8bd5dfa1..df8ba9db9d 100644
--- a/lib/Target/Mips/MipsDSPInstrInfo.td
+++ b/lib/Target/Mips/MipsDSPInstrInfo.td
@@ -548,10 +548,10 @@ class ADDQ_S_W_DESC : ADDU_QB_DESC_BASE<"addq_s.w", int_mips_addq_s_w,
class SUBQ_S_W_DESC : ADDU_QB_DESC_BASE<"subq_s.w", int_mips_subq_s_w,
NoItinerary, CPURegs, CPURegs>;
-class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", int_mips_addsc, NoItinerary,
+class ADDSC_DESC : ADDU_QB_DESC_BASE<"addsc", null_frag, NoItinerary,
CPURegs, CPURegs>, IsCommutable;
-class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", int_mips_addwc, NoItinerary,
+class ADDWC_DESC : ADDU_QB_DESC_BASE<"addwc", null_frag, NoItinerary,
CPURegs, CPURegs>,
IsCommutable, UseDSPCtrl;
@@ -1247,6 +1247,10 @@ def : DSPBinPat<ADDU_QB, v4i8, int_mips_addu_qb>;
def : DSPBinPat<ADDU_QB, v4i8, add>;
def : DSPBinPat<SUBU_QB, v4i8, int_mips_subu_qb>;
def : DSPBinPat<SUBU_QB, v4i8, sub>;
+def : DSPBinPat<ADDSC, i32, int_mips_addsc>;
+def : DSPBinPat<ADDSC, i32, addc>;
+def : DSPBinPat<ADDWC, i32, int_mips_addwc>;
+def : DSPBinPat<ADDWC, i32, adde>;
// Extr patterns.
class EXTR_W_TY1_R2_Pat<SDPatternOperator OpNode, Instruction Instr> :