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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 19:58:23 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-04-22 19:58:23 +0000 |
| commit | d597263b9442923bacc24f26a8510fb69f992864 (patch) | |
| tree | 701478fef64be3c439f5d1cd02ef6054003fe009 /lib/Target/Mips/MipsDSPInstrInfo.td | |
| parent | 6804971dcfbba1dcf7b0f8335588ba2ab6b0f073 (diff) | |
| download | llvm-d597263b9442923bacc24f26a8510fb69f992864.tar.gz llvm-d597263b9442923bacc24f26a8510fb69f992864.tar.bz2 llvm-d597263b9442923bacc24f26a8510fb69f992864.tar.xz | |
[mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180039 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsDSPInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsDSPInstrInfo.td | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 6790a27983..23c6a0592d 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -1288,18 +1288,18 @@ def : DSPBinPat<ADDWC, i32, adde>; // Shift immediate patterns. class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node, - ImmLeaf Imm, Predicate Pred = HasDSP> : + SDPatternOperator Imm, Predicate Pred = HasDSP> : DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>; -def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>; -def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>; -def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>; +def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>; +def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>; +def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>; def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>; def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>; def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>; -def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>; -def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>; -def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>; +def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>; +def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>; +def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>; def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>; def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>; def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>; |