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authorCraig Topper <craig.topper@gmail.com>2012-04-20 07:30:17 +0000
committerCraig Topper <craig.topper@gmail.com>2012-04-20 07:30:17 +0000
commit420761a0f193e87d08ee1c51b26bba23ab4bac7f (patch)
tree55aa0936b18927fe72fb4806eeab177b42c2f9cd /lib/Target/Mips/MipsISelDAGToDAG.cpp
parentc909950c384e8234a7b3c5a76b7f79e3f7012ceb (diff)
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Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsISelDAGToDAG.cpp')
-rw-r--r--lib/Target/Mips/MipsISelDAGToDAG.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index f0651c6131..6e5bad7f15 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -134,7 +134,8 @@ void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
else {
const TargetRegisterClass *RC;
RC = Subtarget.isABI_N64() ?
- Mips::CPU64RegsRegisterClass : Mips::CPURegsRegisterClass;
+ (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
+ (const TargetRegisterClass*)&Mips::CPURegsRegClass;
V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC);