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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 22:58:56 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-20 22:58:56 +0000 |
| commit | 3531db14c61957e7ad00ce972e9685864c3887da (patch) | |
| tree | 2a687704f457441cc8e5b22d42318e8863c80a9a /lib/Target/Mips/MipsInstrFPU.td | |
| parent | 5f560af5411fe4e9f62d4563a74f836b1dae3eae (diff) | |
| download | llvm-3531db14c61957e7ad00ce972e9685864c3887da.tar.gz llvm-3531db14c61957e7ad00ce972e9685864c3887da.tar.bz2 llvm-3531db14c61957e7ad00ce972e9685864c3887da.tar.xz | |
[mips] Define register class FGRH32 for the high half of the 64-bit floating
point registers. We will need this register class later when we add
definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices
sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 28fdbf5daa..92a828c9f2 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -576,7 +576,7 @@ let Predicates = [IsFP64bit, HasStdEnc] in { def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D64_W GPR32Opnd:$src)>; def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)), - (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_32)>; + (EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>; def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)), (PseudoCVT_D64_L GPR64Opnd:$src)>; |