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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-08-17 20:16:42 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-08-17 20:16:42 +0000 |
commit | 72e9b6aeb48d9496bac9db8b02c88a618b464588 (patch) | |
tree | 4d9fc91cc8ee09c3e890cf494337717ec5ee7d56 /lib/Target/Mips/MipsInstrFPU.td | |
parent | 168843c0137ad67c24a3930244a9c5f60add320d (diff) | |
download | llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.tar.gz llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.tar.bz2 llvm-72e9b6aeb48d9496bac9db8b02c88a618b464588.tar.xz |
Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 3e78c45643..df45df46ac 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -103,7 +103,7 @@ class FPStore<bits<6> op, string opstr, RegisterClass RC, Operand MemOpnd>: class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC, RegisterClass PRC, SDPatternOperator FOp = null_frag>: FFMemIdx<funct, (outs DRC:$fd), (ins PRC:$base, PRC:$index), - !strconcat(opstr, "\t$fd, $index($base)"), + !strconcat(opstr, "\t$fd, ${index}(${base})"), [(set DRC:$fd, (FOp (add PRC:$base, PRC:$index)))]> { let fs = 0; } @@ -112,7 +112,7 @@ class FPIdxLoad<bits<6> funct, string opstr, RegisterClass DRC, class FPIdxStore<bits<6> funct, string opstr, RegisterClass DRC, RegisterClass PRC, SDPatternOperator FOp= null_frag>: FFMemIdx<funct, (outs), (ins DRC:$fs, PRC:$base, PRC:$index), - !strconcat(opstr, "\t$fs, $index($base)"), + !strconcat(opstr, "\t$fs, ${index}(${base})"), [(FOp DRC:$fs, (add PRC:$base, PRC:$index))]> { let fd = 0; } |