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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-13 01:32:36 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-13 01:32:36 +0000 |
commit | 89828a6a563426edda0e30384997b2b24be6bb12 (patch) | |
tree | 9f9ca1ae40c36f64130f0fd6d52c33c2382c2f99 /lib/Target/Mips/MipsInstrFPU.td | |
parent | 2b1a50cfdb2db28605fc9834310890160c29be4f (diff) | |
download | llvm-89828a6a563426edda0e30384997b2b24be6bb12.tar.gz llvm-89828a6a563426edda0e30384997b2b24be6bb12.tar.bz2 llvm-89828a6a563426edda0e30384997b2b24be6bb12.tar.xz |
[mips] Modify definitions of floating point branch instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170076 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
-rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 182f2e9150..878e6b2d1f 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -273,6 +273,17 @@ class SWXC1_FT<string opstr, RegisterClass DRC, RegisterClass PRC, !strconcat(opstr, "\t$fs, ${index}(${base})"), [(OpNode DRC:$fs, (add PRC:$base, PRC:$index))], Itin, FrmFI>; +class BC1F_FT<string opstr, InstrItinClass Itin, + SDPatternOperator Op = null_frag> : + InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), + [(MipsFPBrcond Op, bb:$offset)], Itin, FrmFI> { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 1; + let Defs = [AT]; + let Uses = [FCR31]; +} + //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// @@ -495,8 +506,8 @@ let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in } let DecoderMethod = "DecodeBC1" in { -def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">; -def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">; +def BC1F : BC1F_FT<"bc1f", IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>; +def BC1T : BC1F_FT<"bc1t", IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>; } //===----------------------------------------------------------------------===// // Floating Point Flag Conditions |