diff options
| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-16 10:29:42 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-09-16 10:29:42 +0000 |
| commit | e925f7dbbf497412cd0cc3f67b9b96fed0cc3712 (patch) | |
| tree | d437b605c6c2a28eebc0587ab88f8342319ef300 /lib/Target/Mips/MipsInstrFPU.td | |
| parent | 9bc7603750926c15648dae0d31a5451861a0d11e (diff) | |
| download | llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.tar.gz llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.tar.bz2 llvm-e925f7dbbf497412cd0cc3f67b9b96fed0cc3712.tar.xz | |
This patch implements Mips load/store instructions from/to coprocessor 2. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrFPU.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 7aa080ff64..9f7ce9aa72 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -372,6 +372,14 @@ let Predicates = [NotFP64bit, HasStdEnc] in { def SDC1 : SW_FT<"sdc1", AFGR64Opnd, IIFStore, store>, LW_FM<0x3d>; } +/// Cop2 Memory Instructions +let Predicates = [HasStdEnc] in { + def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>; + def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>; + def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>; + def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>; +} + // Indexed loads and stores. let Predicates = [HasFPIdx, HasStdEnc] in { def LWXC1 : LWXC1_FT<"lwxc1", FGR32Opnd, IIFLoad, load>, LWXC1_FM<0>; |