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authorAkira Hatanaka <ahatanaka@mips.com>2013-07-22 18:52:22 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-07-22 18:52:22 +0000
commit0b926427670de6e0ed855ef93f220a3f51ed1eab (patch)
tree3fd497533d84c9c3eb495407208106243b45bc0c /lib/Target/Mips/MipsInstrInfo.td
parentdbbbccc3492aa7f91f21d8902cfb0b766dabb849 (diff)
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[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td3
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 6082a3f9b4..5e2c68744a 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1099,9 +1099,6 @@ def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
def : InstAlias<"move $dst, $src",
(ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
Requires<[NotMips64]>;
-def : InstAlias<"move $dst, $src",
- (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
- Requires<[NotMips64]>;
def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
def : InstAlias<"addu $rs, $rt, $imm",
(ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;