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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-30 20:24:24 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-07-30 20:24:24 +0000 |
| commit | 8838da6587e60a248b07d4db0e874429ad4e9747 (patch) | |
| tree | 0d135272a339a5f984ffd003425234c01979a087 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | ed0a016e80ba3b56d676d665e067dc2fe7f474f7 (diff) | |
| download | llvm-8838da6587e60a248b07d4db0e874429ad4e9747.tar.gz llvm-8838da6587e60a248b07d4db0e874429ad4e9747.tar.bz2 llvm-8838da6587e60a248b07d4db0e874429ad4e9747.tar.xz | |
[mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias that
turns "bal" into "bgezal".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187440 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 83afcce98a..729203d30d 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -635,14 +635,16 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { } -class BAL_FT : - InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { +class BAL_BR_Pseudo<Instruction RealInst> : + PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>, + PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> { let isBranch = 1; let isTerminator = 1; let isBarrier = 1; let hasDelaySlot = 1; let Defs = [RA]; } + // Syscall class SYS_FT<string opstr> : InstSE<(outs), (ins uimm20:$code_), @@ -994,13 +996,12 @@ def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; -def BAL_BR: BAL_FT, BAL_FM; - def JAL : JumpLink<"jal">, FJ<3>; def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; +def BAL_BR : BAL_BR_Pseudo<BGEZAL>; def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; @@ -1104,7 +1105,7 @@ def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), def : InstAlias<"move $dst, $src", (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, Requires<[NotMips64]>; -def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; +def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 1>; def : InstAlias<"addu $rs, $rt, $imm", (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; def : InstAlias<"add $rs, $rt, $imm", |