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authorAkira Hatanaka <ahatanaka@mips.com>2013-08-28 00:55:15 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-08-28 00:55:15 +0000
commita796d90c0ed7ebd5d58fced43c60afc2e9bf6225 (patch)
treea65b85efb4cbecf44cf92e7a1d0a2c7cee637cd5 /lib/Target/Mips/MipsInstrInfo.td
parentbf19dba2d4c7927832d3037c15e0101afb730415 (diff)
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[mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 714c7a8055..5518b8c532 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -279,6 +279,11 @@ def MipsMemAsmOperand : AsmOperandClass {
let ParserMethod = "parseMemOperand";
}
+def PtrRegAsmOperand : AsmOperandClass {
+ let Name = "PtrReg";
+ let ParserMethod = "parsePtrReg";
+}
+
// Address operand
def mem : Operand<iPTR> {
let PrintMethod = "printMemOperand";
@@ -297,6 +302,8 @@ def mem_ea : Operand<iPTR> {
def PtrRC : Operand<iPTR> {
let MIOperandInfo = (ops ptr_rc);
+ let DecoderMethod = "DecodePtrRegisterClass";
+ let ParserMatchClass = PtrRegAsmOperand;
}
// size operand of ext instruction