Added support for fp callee saved registers.

Added fp register clobbering during calls.
Added AsmPrinter support for "fmask", a bitmask that indicates where on the 
stack the fp callee saved registers are.

Fixed the stack frame layout for Mips, now the callee saved regs 
are in the right stack location (a little documentation about how this
stack frame must look like is present in MipsRegisterInfo.cpp).
This was done using the method MipsRegisterInfo::adjustMipsStackFrame
To be more clear, these are examples of what is solves :  

1) FP and RA are also callee saved, and despite they aren't in CSI they 
   must be saved before the fp callee saved registers. 
2) The ABI requires that local varibles are allocated before the callee 
   saved register area, the opposite behavior from the default allocation.
3) CPU and FPU saved register area must be aligned independent of each
   other.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54403 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 0 deletions

diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h
index 2d0436b7a6..808e995b4e 100644
--- a/lib/Target/Mips/MipsRegisterInfo.h
+++ b/lib/Target/Mips/MipsRegisterInfo.h
@@ -36,6 +36,9 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
   /// Get PIC indirect call register
   static unsigned getPICCallReg(void); 
 
+  /// Adjust the Mips stack frame.
+  void adjustMipsStackFrame(MachineFunction &MF) const;
+
   /// Code Generation virtual methods...
   const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;