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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 00:28:19 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 00:28:19 +0000 |
commit | 6a45d681e53a99b4c4f63e0b1664626a596a8151 (patch) | |
tree | 93f2e7b40f4ff7487a536b62da8f6dd2e2531b87 /lib/Target/Mips/MipsRegisterInfo.td | |
parent | 6d37a29588e9a48d81480501f895ac627bf60201 (diff) | |
download | llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.gz llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.bz2 llvm-6a45d681e53a99b4c4f63e0b1664626a596a8151.tar.xz |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsRegisterInfo.td')
-rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 26 |
1 files changed, 6 insertions, 20 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 576110d77c..be78a22662 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -34,9 +34,14 @@ class FPR<bits<5> num, string n> : MipsReg<n> { } // Mips 64-bit (aliased) FPU Registers -class AFPR<bits<5> num, string n, list<Register> subregs> +let Namespace = "Mips" in { +def sub_fpeven : SubRegIndex; +def sub_fpodd : SubRegIndex; +} +class AFPR<bits<5> num, string n, list<Register> subregs> : MipsRegWithSubRegs<n, subregs> { let Num = num; + let SubRegIndices = [sub_fpeven, sub_fpodd]; } //===----------------------------------------------------------------------===// @@ -141,25 +146,6 @@ let Namespace = "Mips" in { } //===----------------------------------------------------------------------===// -// Subregister Set Definitions -//===----------------------------------------------------------------------===// - -let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex; -def sub_fpodd : SubRegIndex; -} - -def : SubRegSet<sub_fpeven, [D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15], - [F0, F2, F4, F6, F8, F10, F12, F14, - F16, F18, F20, F22, F24, F26, F28, F30]>; - -def : SubRegSet<sub_fpodd, [D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9, D10, D11, D12, D13, D14, D15], - [F1, F3, F5, F7, F9, F11, F13, F15, - F17, F19, F21, F23, F25, F27, F29, F31]>; - -//===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// |