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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-31 23:52:55 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-07-31 23:52:55 +0000 |
commit | 71746220d3d1c3e8efba35038ac2ff14b4a4d3ae (patch) | |
tree | 81731141188a20b620b74a7e1fb6dc16c86f0859 /lib/Target/Mips/MipsSEInstrInfo.cpp | |
parent | 8589010e3d1d5a902992a5039cffa9d4116982c5 (diff) | |
download | llvm-71746220d3d1c3e8efba35038ac2ff14b4a4d3ae.tar.gz llvm-71746220d3d1c3e8efba35038ac2ff14b4a4d3ae.tar.bz2 llvm-71746220d3d1c3e8efba35038ac2ff14b4a4d3ae.tar.xz |
Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161093 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSEInstrInfo.cpp')
-rw-r--r-- | lib/Target/Mips/MipsSEInstrInfo.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 11ea7c00da..5f8954ba48 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -248,6 +248,26 @@ unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const { } } +/// Adjust SP by Amount bytes. +void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); + DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); + unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; + unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; + + if (isInt<16>(Amount))// addi sp, sp, amount + BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); + else { // Expand immediate that doesn't fit in 16-bit. + unsigned ATReg = STI.isABI_N64() ? Mips::AT_64 : Mips::AT; + + MBB.getParent()->getInfo<MipsFunctionInfo>()->setEmitNOAT(); + Mips::loadImmediate(Amount, STI.isABI_N64(), *this, MBB, I, DL, false, 0); + BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(ATReg); + } +} + unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const { return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || |