diff options
author | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-07 00:52:30 +0000 |
---|---|---|
committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-09-07 00:52:30 +0000 |
commit | 3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0 (patch) | |
tree | d9f40df9d003dfd83664e55e6f8afc909901cf76 /lib/Target/Mips/MipsSEInstrInfo.cpp | |
parent | d65d2fde4eadcb40e80b361e4cf244c02dcc670b (diff) | |
download | llvm-3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0.tar.gz llvm-3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0.tar.bz2 llvm-3e6758541bb8c143f1f8d3ff550eba3dcc8d22e0.tar.xz |
[mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.
Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSEInstrInfo.cpp')
-rw-r--r-- | lib/Target/Mips/MipsSEInstrInfo.cpp | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 374837e37d..9c31254cf4 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -24,11 +24,6 @@ using namespace llvm; -static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), - cl::desc("Expand double precision loads and " - "stores to their single precision " - "counterparts.")); - MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) : MipsInstrInfo(tm, tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), @@ -294,12 +289,6 @@ bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::ExtractElementF64_64: expandExtractElementF64(MBB, MI, true); break; - case Mips::PseudoLDC1: - expandDPLoadStore(MBB, MI, Mips::LDC1, Mips::LWC1); - break; - case Mips::PseudoSDC1: - expandDPLoadStore(MBB, MI, Mips::SDC1, Mips::SWC1); - break; case Mips::MIPSeh_return32: case Mips::MIPSeh_return64: expandEhReturn(MBB, MI); @@ -484,56 +473,6 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, .addReg(HiReg); } -/// Add 4 to the displacement of operand MO. -static void fixDisp(MachineOperand &MO) { - switch (MO.getType()) { - default: - llvm_unreachable("Unhandled operand type."); - case MachineOperand::MO_Immediate: - MO.setImm(MO.getImm() + 4); - break; - case MachineOperand::MO_GlobalAddress: - case MachineOperand::MO_ConstantPoolIndex: - case MachineOperand::MO_BlockAddress: - case MachineOperand::MO_TargetIndex: - case MachineOperand::MO_ExternalSymbol: - MO.setOffset(MO.getOffset() + 4); - break; - } -} - -void MipsSEInstrInfo::expandDPLoadStore(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned OpcD, unsigned OpcS) const { - // If NoDPLoadStore is false, just change the opcode. - if (!NoDPLoadStore) { - genInstrWithNewOpc(OpcD, I); - return; - } - - // Expand a double precision FP load or store to two single precision - // instructions. - - const TargetRegisterInfo &TRI = getRegisterInfo(); - const MachineOperand &ValReg = I->getOperand(0); - unsigned LoReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_lo); - unsigned HiReg = TRI.getSubReg(ValReg.getReg(), Mips::sub_hi); - - if (!TM.getSubtarget<MipsSubtarget>().isLittle()) - std::swap(LoReg, HiReg); - - // Create an instruction which loads from or stores to the lower memory - // address. - MachineInstrBuilder MIB = genInstrWithNewOpc(OpcS, I); - MIB->getOperand(0).setReg(LoReg); - - // Create an instruction which loads from or stores to the higher memory - // address. - MIB = genInstrWithNewOpc(OpcS, I); - MIB->getOperand(0).setReg(HiReg); - fixDisp(MIB->getOperand(2)); -} - void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { // This pseudo instruction is generated as part of the lowering of |