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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-03 00:05:43 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-11-03 00:05:43 +0000 |
commit | 11a45c214c26bdc49ef58c0eb214df5200867cee (patch) | |
tree | 7d61dd7da91f5665a099673d976410ae00b013f8 /lib/Target/Mips/MipsSERegisterInfo.cpp | |
parent | da15a0ed4cd74f767cc124b65b7b7d9482969318 (diff) | |
download | llvm-11a45c214c26bdc49ef58c0eb214df5200867cee.tar.gz llvm-11a45c214c26bdc49ef58c0eb214df5200867cee.tar.bz2 llvm-11a45c214c26bdc49ef58c0eb214df5200867cee.tar.xz |
[mips] Stop reserving register AT and use register scavenger when a scratch
register is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSERegisterInfo.cpp')
-rw-r--r-- | lib/Target/Mips/MipsSERegisterInfo.cpp | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsSERegisterInfo.cpp b/lib/Target/Mips/MipsSERegisterInfo.cpp index b35d05c563..56b9ba95e5 100644 --- a/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -26,6 +26,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -43,6 +44,16 @@ MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST, const MipsSEInstrInfo &I) : MipsRegisterInfo(ST), TII(I) {} +bool MipsSERegisterInfo:: +requiresRegisterScavenging(const MachineFunction &MF) const { + return true; +} + +bool MipsSERegisterInfo:: +requiresFrameIndexScavenging(const MachineFunction &MF) const { + return true; +} + // This function eliminate ADJCALLSTACKDOWN, // ADJCALLSTACKUP pseudo instructions void MipsSERegisterInfo:: @@ -102,6 +113,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, // - If the frame object is any of the following, its offset must be adjusted // by adding the size of the stack: // incoming argument, callee-saved register location or local variable. + bool IsKill = false; int64_t Offset; Offset = SPOffset + (int64_t)StackSize; @@ -115,16 +127,17 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = II->getDebugLoc(); unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; - unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips::AT; unsigned NewImm; unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm); - BuildMI(MBB, II, DL, TII.get(ADDu), ATReg).addReg(FrameReg).addReg(Reg); + BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) + .addReg(Reg, RegState::Kill); - FrameReg = ATReg; + FrameReg = Reg; Offset = SignExtend64<16>(NewImm); + IsKill = true; } - MI.getOperand(OpNo).ChangeToRegister(FrameReg, false); + MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); MI.getOperand(OpNo + 1).ChangeToImmediate(Offset); } |