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authorBill Wendling <isanbard@gmail.com>2013-06-07 07:04:14 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 07:04:14 +0000
commit41e632d9e1a55d36cb08b0551ad82a13d9137a5e (patch)
tree52d4b47f777e9928012d6028eefa27bedf9f4a12 /lib/Target/Mips/MipsSERegisterInfo.cpp
parented8b5b55a4416286758c5567c2602d2c7d0be585 (diff)
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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183493 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSERegisterInfo.cpp')
-rw-r--r--lib/Target/Mips/MipsSERegisterInfo.cpp9
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/Mips/MipsSERegisterInfo.cpp b/lib/Target/Mips/MipsSERegisterInfo.cpp
index 96967380b2..9763f85956 100644
--- a/lib/Target/Mips/MipsSERegisterInfo.cpp
+++ b/lib/Target/Mips/MipsSERegisterInfo.cpp
@@ -40,9 +40,8 @@
using namespace llvm;
-MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST,
- const MipsSEInstrInfo &I)
- : MipsRegisterInfo(ST), TII(I) {}
+MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
+ : MipsRegisterInfo(ST) {}
bool MipsSERegisterInfo::
requiresRegisterScavenging(const MachineFunction &MF) const {
@@ -119,7 +118,9 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
DebugLoc DL = II->getDebugLoc();
unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
unsigned NewImm;
-
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(
+ MBB.getParent()->getTarget().getInstrInfo());
unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
.addReg(Reg, RegState::Kill);