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| author | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:51:11 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanak@gmail.com> | 2011-04-15 21:51:11 +0000 |
| commit | 4552c9a3b34ad9b2085635266348d0d9b95514a6 (patch) | |
| tree | d7e5b6178d0738dff93e314e346515728077158f /lib/Target/Mips/MipsSchedule.td | |
| parent | 0cb11ac32fc09c5db42fb801db242ac9fb51f6b1 (diff) | |
| download | llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.gz llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.bz2 llvm-4552c9a3b34ad9b2085635266348d0d9b95514a6.tar.xz | |
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129612 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSchedule.td')
| -rw-r--r-- | lib/Target/Mips/MipsSchedule.td | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/Mips/MipsSchedule.td b/lib/Target/Mips/MipsSchedule.td index bb7d5f1a88..00be8ee944 100644 --- a/lib/Target/Mips/MipsSchedule.td +++ b/lib/Target/Mips/MipsSchedule.td @@ -1,21 +1,21 @@ -//===- MipsSchedule.td - Mips Scheduling Definitions ------*- tablegen -*-===// +//===- MipsSchedule.td - Mips Scheduling Definitions -------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Functional units across Mips chips sets. Based on GCC/Mips backend files. -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// def ALU : FuncUnit; def IMULDIV : FuncUnit; -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Instruction Itinerary classes used for Mips -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// def IIAlu : InstrItinClass; def IILoad : InstrItinClass; def IIStore : InstrItinClass; @@ -37,9 +37,9 @@ def IIFsqrtDouble : InstrItinClass; def IIFrecipFsqrtStep : InstrItinClass; def IIPseudo : InstrItinClass; -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// // Mips Generic instruction itineraries. -//===---------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<IIAlu , [InstrStage<1, [ALU]>]>, InstrItinData<IILoad , [InstrStage<3, [ALU]>]>, |