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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-06 23:08:38 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-08-06 23:08:38 +0000 |
| commit | 1858786285139b87961d9ca08de91dcd59364afb (patch) | |
| tree | 2e0913c83c690b1c3d8e2e0604b0681e3b2d15a1 /lib/Target/Mips/MipsSubtarget.cpp | |
| parent | 3492eefa4b2509c87598678a6977074a3f6a50e6 (diff) | |
| download | llvm-1858786285139b87961d9ca08de91dcd59364afb.tar.gz llvm-1858786285139b87961d9ca08de91dcd59364afb.tar.bz2 llvm-1858786285139b87961d9ca08de91dcd59364afb.tar.xz | |
[mips] Rename register classes CPURegs and CPU64Regs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 259e68df32..541e2ca4da 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -104,7 +104,7 @@ MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, Mode = TargetSubtargetInfo::ANTIDEP_NONE; CriticalPathRCs.clear(); CriticalPathRCs.push_back(hasMips64() ? - &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass); + &Mips::GPR64RegClass : &Mips::GPR32RegClass); return OptLevel >= CodeGenOpt::Aggressive; } |