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| author | Reed Kotler <rkotler@mips.com> | 2013-08-30 19:40:56 +0000 |
|---|---|---|
| committer | Reed Kotler <rkotler@mips.com> | 2013-08-30 19:40:56 +0000 |
| commit | c673f9c6fecb0f828845ada7ea5458f66f896283 (patch) | |
| tree | c01992b0db5afefcd839eec44580f99e8406a9a2 /lib/Target/Mips/MipsSubtarget.h | |
| parent | 846b31d74aa673a178f57f9d47f366d8ddb756d3 (diff) | |
| download | llvm-c673f9c6fecb0f828845ada7ea5458f66f896283.tar.gz llvm-c673f9c6fecb0f828845ada7ea5458f66f896283.tar.bz2 llvm-c673f9c6fecb0f828845ada7ea5458f66f896283.tar.xz | |
Fix a problem with dual mips16/mips32 mode. When the underlying processor
has hard float, when you compile the mips32 code you have to make sure
that it knows to compile any mips32 routines as hard float. I need to clean
up the way mips16 hard float is specified but I need to first think through
all the details. Mips16 always has a form of soft float, the difference being
whether the underlying hardware has floating point. So it's not really
necessary to pass the -soft-float to llvm since soft-float is always true
for mips16 by virtue of the fact that it will not register floating point
registers. By using this fact, I can simplify the way this is all handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189690 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsSubtarget.h')
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 03bef69fb5..140ddde045 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -192,6 +192,8 @@ public: bool hasStandardEncoding() const { return !inMips16Mode(); } + bool mipsSEUsesSoftFloat() const; + /// Features related to the presence of specific instructions. bool hasSEInReg() const { return HasSEInReg; } bool hasCondMov() const { return HasCondMov; } |