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| author | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-30 02:29:43 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2013-10-30 02:29:43 +0000 |
| commit | 99a43d3b8f5cf86b333055a56220c6965fd9ece4 (patch) | |
| tree | a3cdf4d5df34e2b3342e351ce7923a19bbaa0726 /lib/Target/Mips | |
| parent | 62406fdc6f199e4e7df60830be45de4da97b34c7 (diff) | |
| download | llvm-99a43d3b8f5cf86b333055a56220c6965fd9ece4.tar.gz llvm-99a43d3b8f5cf86b333055a56220c6965fd9ece4.tar.bz2 llvm-99a43d3b8f5cf86b333055a56220c6965fd9ece4.tar.xz | |
[mips] Compute stack alignment on the fly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193673 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
| -rw-r--r-- | lib/Target/Mips/Mips.td | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsSubtarget.h | 4 |
3 files changed, 3 insertions, 7 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 0581d84a05..b8e3f39256 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -30,12 +30,10 @@ def MipsInstrInfo : InstrInfo; // Mips Subtarget features // //===----------------------------------------------------------------------===// -def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16", - "Set stack alignment to 16-bytes.">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", - "Support 64-bit FP registers.", [StackAlign16]>; + "Support 64-bit FP registers.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 07957ef61b..0a81072b08 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -72,7 +72,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), - StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM) + RM(_RM), OverrideMode(NoOverride), TM(_TM) { std::string CPUName = CPU; if (CPUName.empty()) diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 378fc00f45..7c175537a7 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -116,8 +116,6 @@ protected: // HasMSA -- supports MSA ASE. bool HasMSA; - unsigned StackAlignment; - InstrItineraryData InstrItins; // The instance to the register info section object @@ -219,7 +217,7 @@ public: // static bool useConstantIslands(); - unsigned stackAlignment() const { return StackAlignment; } + unsigned stackAlignment() const { return isFP64bit() ? 16 : 8; } // Grab MipsRegInfo object const MipsReginfo &getMReginfo() const { return MRI; } |