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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-10-19 21:14:34 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-10-19 21:14:34 +0000 |
commit | 01a75c46e3292c1a66b577b5a6b7510a1867afdd (patch) | |
tree | c5f45f3e9cb4b49855537371bb9cbc74d06fe9b8 /lib/Target/Mips | |
parent | 1f027135a89f6673d48e709ec5053809ab157bc3 (diff) | |
download | llvm-01a75c46e3292c1a66b577b5a6b7510a1867afdd.tar.gz llvm-01a75c46e3292c1a66b577b5a6b7510a1867afdd.tar.bz2 llvm-01a75c46e3292c1a66b577b5a6b7510a1867afdd.tar.xz |
[mips] Add tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166338 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips')
-rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 1 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 11 |
2 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 99a9f25abd..ed0ea0e849 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -177,6 +177,7 @@ def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>; } let DecoderNamespace = "Mips64" in def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; +def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall; let DecoderNamespace = "Mips64" in { /// Multiply and Divide Instructions. diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index f4fd8913d0..82a15efa46 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -191,6 +191,15 @@ class IsCall { bit isCall = 1; } +class IsTailCall { + bit isCall = 1; + bit isTerminator = 1; + bit isReturn = 1; + bit isBarrier = 1; + bit hasExtraSrcRegAllocReq = 1; + bit isCodeGenOnly = 1; +} + //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// @@ -1013,6 +1022,8 @@ def JAL : JumpLink<0x03, "jal">; def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; +def TAILCALL : JumpFJ<0x02, "j", br>, IsTailCall; +def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; def RET : RetBase<CPURegs>; |