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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:53:27 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-03-26 10:53:27 +0000 |
commit | 3b2552933642c19ce5e8836d82c26c562910e239 (patch) | |
tree | fa94d1abba258b889772f6b15f96f7c5f2b153a9 /lib/Target/PowerPC/InstPrinter | |
parent | e8680da874631c0531872c83d6643e05bbefebd1 (diff) | |
download | llvm-3b2552933642c19ce5e8836d82c26c562910e239.tar.gz llvm-3b2552933642c19ce5e8836d82c26c562910e239.tar.bz2 llvm-3b2552933642c19ce5e8836d82c26c562910e239.tar.xz |
PowerPC: Simplify BLR pattern.
The BLR pattern cannot be recognized by the asm parser in its current form.
This complexity is due to an apparent attempt to enable conditional BLR
variants. However, none of those can ever be generated by current code;
the pattern is only ever created using the default "pred" operand.
To simplify the pattern and allow it to be recognized by the parser,
this commit removes those attempts at conditional BLR support.
When we later come back to actually add real conditional BLR, this
should probably be done via a fully generic conditional branch pattern.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178002 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/InstPrinter')
-rw-r--r-- | lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index 3d583060d1..985c343696 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -115,7 +115,6 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, if (StringRef(Modifier) == "cc") { switch ((PPC::Predicate)Code) { - case PPC::PRED_ALWAYS: return; // Don't print anything for always. case PPC::PRED_LT: O << "lt"; return; case PPC::PRED_LE: O << "le"; return; case PPC::PRED_EQ: O << "eq"; return; @@ -129,8 +128,6 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, assert(StringRef(Modifier) == "reg" && "Need to specify 'cc' or 'reg' as predicate op modifier!"); - // Don't print the register for 'always'. - if (Code == PPC::PRED_ALWAYS) return; printOperand(MI, OpNo+1, O); } |