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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-05 12:22:36 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-05 12:22:36 +0000
commit23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df (patch)
tree93954d1ea2e8230d74fceb259dbc4566b6ea8901 /lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
parent87b8a7f9996ee7463b787fc85394287de903c7d7 (diff)
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[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp')
-rw-r--r--lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp3
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
index b37a17933c..4f999a1534 100644
--- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
+++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
@@ -30,7 +30,6 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
case FK_Data_2:
case FK_Data_4:
case FK_Data_8:
- case PPC::fixup_ppc_tlsreg:
case PPC::fixup_ppc_nofixup:
return Value;
case PPC::fixup_ppc_brcond14:
@@ -64,7 +63,6 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
return 4;
case FK_Data_8:
return 8;
- case PPC::fixup_ppc_tlsreg:
case PPC::fixup_ppc_nofixup:
return 0;
}
@@ -101,7 +99,6 @@ public:
{ "fixup_ppc_brcond14abs", 16, 14, 0 },
{ "fixup_ppc_half16", 0, 16, 0 },
{ "fixup_ppc_half16ds", 0, 14, 0 },
- { "fixup_ppc_tlsreg", 0, 0, 0 },
{ "fixup_ppc_nofixup", 0, 0, 0 }
};