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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:49:18 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-05 05:49:18 +0000 |
| commit | 1abaf907b6aff6e468cb838fa40e0ec6cc5ece24 (patch) | |
| tree | 8eeb038f7d25daa7ed604612ceab9f8d2b468691 /lib/Target/PowerPC/PPC.td | |
| parent | fad7aa792a9d642cdc9345c9cffa2b9407e2635e (diff) | |
| download | llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.gz llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.bz2 llvm-1abaf907b6aff6e468cb838fa40e0ec6cc5ece24.tar.xz | |
Add a SchedMachineModel for the PPC G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 82a69b4769..389216278e 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -139,12 +139,12 @@ def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE]>; def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE]>; -def : Processor<"970", G5Itineraries, +def : ProcessorModel<"970", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */]>; -def : Processor<"g5", G5Itineraries, +def : ProcessorModel<"g5", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureFRES, FeatureFRSQRTE, @@ -171,37 +171,37 @@ def : ProcessorModel<"a2q", PPCA2Model, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, FeatureQPX]>; -def : Processor<"pwr3", G5Itineraries, +def : ProcessorModel<"pwr3", G5Model, [DirectivePwr3, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, FeatureSTFIWX, Feature64Bit]>; -def : Processor<"pwr4", G5Itineraries, +def : ProcessorModel<"pwr4", G5Model, [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit]>; -def : Processor<"pwr5", G5Itineraries, +def : ProcessorModel<"pwr5", G5Model, [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, Feature64Bit]>; -def : Processor<"pwr5x", G5Itineraries, +def : ProcessorModel<"pwr5x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, FeatureFPRND, Feature64Bit]>; -def : Processor<"pwr6", G5Itineraries, +def : ProcessorModel<"pwr6", G5Model, [DirectivePwr6, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>; -def : Processor<"pwr6x", G5Itineraries, +def : ProcessorModel<"pwr6x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureFPRND, Feature64Bit]>; -def : Processor<"pwr7", G5Itineraries, +def : ProcessorModel<"pwr7", G5Model, [DirectivePwr7, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, @@ -210,7 +210,7 @@ def : Processor<"pwr7", G5Itineraries, FeaturePOPCNTD, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; -def : Processor<"ppc64", G5Itineraries, +def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, |