Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 38 insertions, 0 deletions

diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td
new file mode 100644
index 0000000000..05f0d3715b
--- /dev/null
+++ b/lib/Target/PowerPC/PPC.td
@@ -0,0 +1,38 @@
+//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
+// 
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// 
+//===----------------------------------------------------------------------===//
+//
+// This is the top level entry point for the PowerPC target.
+//
+//===----------------------------------------------------------------------===//
+
+// Get the target-independent interfaces which we are implementing.
+//
+include "../Target.td"
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "PowerPCRegisterInfo.td"
+include "PowerPCInstrInfo.td"
+
+def PPC : Target {
+  // Pointers on PPC are 32-bits in size.
+  let PointerType = i32;
+
+  // According to the Mach-O Runtime ABI, these regs are nonvolatile across
+  // calls
+  let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
+    R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
+    F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
+    F30, F31, CR2, CR3, CR4, LR];
+
+  // Pull in Instruction Info:
+  let InstructionSet = PowerPCInstrInfo;
+}