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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 13:29:47 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-28 13:29:47 +0000 |
| commit | c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff (patch) | |
| tree | b2fcb51be8d19be85b7154477017f83ee096e6da /lib/Target/PowerPC/PPC.td | |
| parent | f464481db0c3b5404004b510921ca454803fd1d0 (diff) | |
| download | llvm-c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff.tar.gz llvm-c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff.tar.bz2 llvm-c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff.tar.xz | |
Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC.td')
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 992913602a..dfab690a9d 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -61,6 +61,8 @@ def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true", "Enable the stfiwx instruction">; def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true", "Enable the isel instruction">; +def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true", + "Enable the popcnt[dw] instructions">; def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true", "Enable Book E instructions">; def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", @@ -79,7 +81,6 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true", // LFIWAX p6, p6x, p7 lfiwax // LFIWZX p7 lfiwzx // POPCNTB p5 through p7 popcntb and related instructions -// POPCNTD p7 popcntd and related instructions // RECIP_PREC p6, p6x, p7 higher precision reciprocal estimates // VSX p7 vector-scalar instruction set @@ -131,12 +132,13 @@ def : ProcessorModel<"e5500", PPCE5500Model, def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureISEL, - Feature64Bit + FeaturePOPCNTD, Feature64Bit /*, Feature64BitRegs */]>; def : Processor<"a2q", PPCA2Itineraries, [DirectiveA2, FeatureBookE, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureISEL, - Feature64Bit /*, Feature64BitRegs */, + FeaturePOPCNTD, Feature64Bit + /*, Feature64BitRegs */, FeatureQPX]>; def : Processor<"pwr3", G5Itineraries, [DirectivePwr3, FeatureAltivec, FeatureMFOCRF, @@ -160,7 +162,8 @@ def : Processor<"pwr6x", G5Itineraries, def : Processor<"pwr7", G5Itineraries, [DirectivePwr7, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, - FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>; + FeatureISEL, FeaturePOPCNTD, Feature64Bit + /*, Feature64BitRegs */]>; def : Processor<"ppc", G3Itineraries, [Directive32]>; def : Processor<"ppc64", G5Itineraries, [Directive64, FeatureAltivec, |