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authorChris Lattner <sabre@nondot.org>2010-11-16 00:55:51 +0000
committerChris Lattner <sabre@nondot.org>2010-11-16 00:55:51 +0000
commitb69cdfa6f3d5a0661354e744a11caa7b3342b83e (patch)
tree9aa1e2e5b83cb6c5bbb8c26c1dd931df914e4bb7 /lib/Target/PowerPC/PPCCodeEmitter.cpp
parentb55e91e08738b804f17109a49881e51b69e91299 (diff)
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relax an assertion a bit, allowing the GPR argument of
these instructions to be encoded with getMachineOpValue. This unbreaks ExecutionEngine/2003-01-04-ArgumentBug.ll when running on a G5 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCCodeEmitter.cpp')
-rw-r--r--lib/Target/PowerPC/PPCCodeEmitter.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 7c5fa7d5e4..42232a0753 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -246,7 +246,10 @@ unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
const MachineOperand &MO) const {
if (MO.isReg()) {
- assert(MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF);
+ // MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
+ // The GPR operand should come through here though.
+ assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
+ MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
return PPCRegisterInfo::getRegisterNumbering(MO.getReg());
}